Submit a design
You hand PPABench a chip — a core that drops into the locked user_project_wrapper —
and the harness does the rest: hardens it to a GDS, runs the hidden testbench, and produces one scorecard.
There are two tiers.
What you deliver
For any track, your design must implement the locked chassis contract: top module
user_project_wrapper with the exact pinout (Wishbone control, QSPI flash, UART, byte-stream,
done/error), reset and clock as specified, and — for the MCU tracks — boot from the
provided QSPI flash image. See each benchmark page (MCU A,
MCU B, JPEG) for the per-task spec.
Tier 1 — Collateral (artifact submission)
The basic flow, like SWE-bench. You run your agent / flow locally and submit the artifacts:
- your wrapper RTL (and any user RTL), plus constraints;
- optionally a pre-hardened GDS + metrics (the harness re-runs the deterministic grade to confirm).
The harness re-hardens and re-simulates from your sources, so the score is reproducible and not self-reported.
Tier 2 — Verified (Docker)
The anti-contamination tier. You ship a Docker image that honors an agentic contract: it reads the prompt from a mounted input and writes the artifact bundle to a mounted output. PPABench runs your container server-side on a held-out prompt, then runs the same deterministic grade. Because the prompt is held out and time-windowed, a Verified result can't be overfit to a public task.
How it's graded
Both tiers produce one scorecard from two halves:
- Harden → area, fmax, power (dynamic + leakage), DRC-clean, LVS-match.
- Hidden testbench → functional correctness over random trials + externally-counted cycles + energy.
Pass requires PPA caps + functional_ok + timing_met + DRC + LVS. Passing
designs are ranked by the energy / area / performance figures of merit. See Details.