PPABench
A benchmark that verifies agentic chip design. A prompt becomes a core hardened into the fixed OpenFrame / chipignite chassis, then graded on both halves of a real chip: harden (PPA — area, power, fmax, DRC, LVS) and a hidden testbench (functional correctness + energy). Cycles are counted externally at the wrapper boundary and inputs are randomized per run, so results cannot be faked or precomputed.
PDK sky130 HD
chassis OpenFrame / chipignite
anti-cheat external cycles + random input
v 0.1 · pre-MVP
MCU A Fixed RV32I — CRC32
graded on IPC + energy/instruction · ranked by EDP. Lower energy ranks higher.| # | Submission | Func | Cycles | IPC | CPI | pJ/cycle | Energy nJ | pJ/instr | Area µm² | fmax MHz | EDP nJ·µs |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | picosoc · reference baseline | ✓ | 1,433,997 | 0.0120 | 83.23 | 3.54 | 5,076 | 295 | 3,810 | 88.5 | 1.46e8 |
Reference baseline (picorv32). Functional + cycles from live Verilator/cocotb (cycles counted
externally, start→done). Energy = P·cycles/f @ 50 MHz. See MCU A details →
MCU B Open ISA — AES-128-CBC (random input)
verify-by-result over random key/plaintext · ranked by energy/byte.| # | Submission | Func | Cycles | Cyc/block | pJ/cycle | Energy nJ | pJ/byte | Area µm² | fmax MHz | Trials |
|---|---|---|---|---|---|---|---|---|---|---|
| 1 | picosoc · reference baseline | ✓ | 1,088,825 | 272,206 | 3.54 | 3,854 | 60,226 | 3,810 | 88.5 | 3/3 |
3 fresh random seeds, all exact-match vs software golden. Held-out variant (SipHash-2-4) used
off-leaderboard for contamination checks. See MCU B details →
JPEG Streaming baseline JPEG compressor
pixel stream in → JPEG bytes out · graded on PSNR / bitrate + PPA + throughput.No submissions yet — reference run pending.
Read the JPEG benchmark spec →
Read the JPEG benchmark spec →
PPABench v0.1 · reference baseline picosoc/picorv32 on sky130 HD · grading: harden (OpenROAD/Magic/netgen) + hidden cocotb TB · github.com/balbekov